ADZS-BF527-EZLITE【PDF 8/88 页】BOARD EVAL ADSP-BF527

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Table 3. System Interrupt Controller (SIC) (Continued)

General Purpose

Default

Peripheral Interrupt Event

OTP Memory Interrupt

GP Counter

DMA Channel 1 (MAC RX/HOSTDP)

Port H Interrupt A

DMA Channel 2 (MAC TX/NFC)

Port H Interrupt B

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

Timer 6

Timer 7

Port G Interrupt A

Port G Interrupt B

MDMA Stream 0

MDMA Stream 1

Software Watchdog Timer

Port F Interrupt A

Port F Interrupt B

SPI Status

NFC Status

HOSTDP Status

Host Read Done

Reserved

USB_INT0 Interrupt

USB_INT1 Interrupt

USB_INT2 Interrupt

USB_DMAINT Interrupt

Interrupt (at RESET)

IVG11

IVG11

IVG11

IVG11

IVG11

IVG11

IVG12

IVG12

IVG12

IVG12

IVG12

IVG12

IVG12

IVG12

IVG12

IVG12

IVG13

IVG13

IVG13

IVG13

IVG13

IVG7

IVG7

IVG7

IVG7

IVG10

IVG10

IVG10

IVG10

IVG10

Peripheral Interrupt ID

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

Core Interrupt ID

4

4

4

4

4

4

5

5

5

5

5

5

5

5

5

5

6

6

6

6

6

0

0

0

0

3

3

3

3

3

SIC Registers

IAR3 IMASK0, ISR0, IWR0

IAR3 IMASK0, ISR0, IWR0

IAR3 IMASK0, ISR0, IWR0

IAR3 IMASK0, ISR0, IWR0

IAR3 IMASK0, ISR0, IWR0

IAR3 IMASK0, ISR0, IWR0

IAR4 IMASK1, ISR1, IWR1

IAR4 IMASK1, ISR1, IWR1

IAR4 IMASK1, ISR1, IWR1

IAR4 IMASK1, ISR1, IWR1

IAR4 IMASK1, ISR1, IWR1

IAR4 IMASK1, ISR1, IWR1

IAR4 IMASK1, ISR1, IWR1

IAR4 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

Event Control

The processor provides a very flexible mechanism to control the

processing of events. In the CEC, three registers are used to

coordinate and control events. Each register is 16 bits wide.

? CEC interrupt latch register (ILAT) — Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and cleared when the

event has been accepted into the system. This register is

updated automatically by the controller, but it may be writ-

ten only when its corresponding IMASK bit is cleared.

? CEC interrupt mask register (IMASK) — Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register may be read or

written while in supervisor mode. (Note that general-

purpose interrupts can be globally enabled and disabled

with the STI and CLI instructions, respectively.)

? CEC interrupt pending register (IPEND) — The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing

three pairs of 32-bit interrupt control and status registers. Each

register contains a bit corresponding to each of the peripheral

interrupt events shown in Table 3 on Page 7 .

? SIC interrupt mask registers (SIC_IMASKx) — Control the

masking and unmasking of each peripheral interrupt event.

When a bit is set in these registers, that peripheral event is

Rev. D | Page 8 of 88 | July 2013

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